The paper Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation by Ehsan K.Ardestani, Francisco J. Mesa-Martinez, Gabriel Southern, Elnaz Ebrahimi, and Jose Renau will appear in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). It gives an overview of the role of sampling in thermal evaluation of processors. ESESC provides the simulation infrastructure for this paper.

Abstract

Power densities in modern processors induce thermal issues which limit performance. Power and thermal models add complexity to architectural simulators, limiting the depth of analysis. Prohibitive execution time overheads may be circumvented using sampling techniques. While these approaches work well when characterizing processor performance, they introduce new challenges when applied to the thermal domain. This work aims to improve the accuracy and performance of sampled thermal simulation at the architectural level.

To the best of our knowledge, this paper is the first to evaluate the impact of statistical sampling on thermal metrics through direct temperature measurements performed at run time. Experiments confirm that sampling can accurately estimate certain thermal metrics. However, extra consideration needs to be taken into account to preserve the accuracy of temperature estimation in a sampled simulation. Mainly because, on average, thermal phases are much longer than performance phases. Based on these insights, we introduce a framework that extends statistical sampling techniques, used at the performance and power stages, to the thermal domain. The resulting technique yields an integrated performance, power, and temperature simulator that maintains accuracy while reducing simulation time by orders of magnitude. In particular, this work shows how dynamic frequency and voltage adaptations can be evaluated in a statistically sampled simulation. We conclude by showing how the increased simulation speed benefits architects in the exploration of the design space.

ESESC is first introduced in the HPCA 2013 paper ESESC: A Fast Multicore Simulator Using Time-Based Sampling by Ehsan K.Ardestani, and Jose Renau. This paper is the first to propose the concept of Time-Based Sampling (TBS) to solve the issues related to evaluation of multithreaded applications.

Abstract

Architects rely on simulation in their exploration of the design space. However, slow simulation speed caps their productivity and limits the depth of their exploration. Sampling has been a commonly used remedy. While sampling is shown to be an effective technique for single core processors, its application has been limited to simulation of multiprogram, throughput applications only. This work presents Time-Based Sampling (TBS), a framework that is the first to enable sampling in simulation of multicore processors with virtually no limitation in terms of application type (multiprogrammed or multithreaded), number of cores, homogeneity or heterogeneity of the simulated configuration (4.99% error averaged across all the evaluated configurations). TBS also is the first to enable integrated power and temperature evaluation in statistically sampled simulation of multicore systems (with 5.5% and 2.4% error on average, respectively). We implement an architectural simulator based on TBS, called ESESC, that provides a holistic set of tools for a fair evaluation of different architectures.

ESESC is used by the ISLPED 2012 paper Thermal-Aware Sampling in Architectural Simulation by Ehsan K.Ardestani, Elnaz Ebrahimi, Gabriel Southern, and Jose Renau explains how to perform thermal sampling with ESESC for a single core configuration.

Abstract

Thermal behavior of modern processors is a first-order design constraint. However, accurate estimation of thermal behavior is time consuming, and techniques for accelerating performance simulations often yield inaccurate results when directly applied to thermal simulation, or do not reduce the thermal computation at all. This paper is the first to propose thermal sampling techniques. It can be integrated with existing phase-based and statistical-based architectural simulator sampling. The resulting simulator can perform accurate performance, power, and thermal characterization at close to 30 MIPS, on average, instead of 5 MIPS for the fastest sampling technique without thermal-aware.